The present invention relates to analog-to-digital converters and particularly to analog-to-digital converters having a very high operating clock frequency.
Conventional high-speed, analog-to-digital converters (xe2x80x9cADCsxe2x80x9d) commonly employ a full flash architecture in which the analog-to-digital conversion is done in parallel by using approximately 2N voltage comparators. An input voltage and fractional portions of a reference voltage are applied simultaneously to each comparator. The fractional portions of the reference voltage are obtained by dividing the reference voltage into equal increments by resistors. The output of each comparator is generally applied to a decoder which decodes such received inputs into a multi-bit digital output representative of the input voltage.
A block diagram of a flash ADC is illustrated in FIG. 5. One problem with such ADCs is that the comparators of the ADCs can have large offsets which generate errors in the digital output. During the auto-zero cycle, the comparator""s output is connected to its input through switch 1702. The capacitor 1704 is connected to the resistance ladder 1706 through switch 1712 instead of the output of the sample-and-hold circuit 1710. This stores both the reference level and the offset information on the capacitor 1704 so that the sample-and-hold circuit 1710 is reconnected to the capacitor 1704 through switch 1708. The input to the comparator 1714 is now equal to the output of the sample-and-hold circuit 1710 minus the reference voltage and minus the comparator offset. One problem with the technique corresponding to the circuit illustrated in FIG. 5 is that the switch 1708 connecting the sample-and-hold circuit 1710 to the coupling capacitor 1704 forms a low-pass RC filter with the input capacitance of the comparator 1714. This limits the bandwidth of the sample-and-hold circuit 1710. One solution to this problem is to use a pass transistor with a high width-to-length ratio and a high gate drive. However, with a low supply voltage that are currently available, this becomes more difficult. With an ADC to operate in the 1 Gbit range, this solution has been identified as one of the bottlenecks that ultimately limits the speed of the ADC. Thus, it is necessary to eliminate the low-pass RC filter.
The comparators that are described above are normally implemented using conventional auto-zero voltage comparators. An auto-zero voltage comparator generally requires a two-phase clock for auto-zeroing in the first phase and for actual signal comparison in the second phase. However, such two-phase design limits the maximum achievable operating frequency to a factor of two lower than otherwise possible, other factors being equal, if non-auto-zero voltage comparators are employed.
The present invention provides an analog-to-digital converter without a switch between the sample-and-hold circuit and the comparator. This eliminates the RC filter which forms a bottleneck between the sample-and-hold circuit and the rest of the ADC. As a consequence, the speed of the ADC can be increased.